Compiler mistakenly reorders and combines conditional definitions of volatile objects

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    • Type: Bug
    • Resolution: Fixed
    • Priority: Medium
    • Code Generation Tools
    • CODEGEN-6909
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      ARM_18.1.0.LTS
       ARM_18.12.0.LTS
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      ARM_18.1.0.LTS  ARM_18.12.0.LTS
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      ARM_18.12.5.LTS
       ARM_18.1.8.LTS*
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      ARM_18.12.5.LTS  ARM_18.1.8.LTS*
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      The compiler has an optimization where if two otherwise-identical instructions have complementary predicates, the two instructions will be combined into a single unconditional instruction. This is common in compiler-generated sequences. The problem is that the compiler should not do this if the instructions access a volatile object and performing the optimization would reorder the accesses. This is exactly the situation in this test case - the user is trying to control the order of volatile accesses with an if statement.
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      The compiler has an optimization where if two otherwise-identical instructions have complementary predicates, the two instructions will be combined into a single unconditional instruction. This is common in compiler-generated sequences. The problem is that the compiler should not do this if the instructions access a volatile object and performing the optimization would reorder the accesses. This is exactly the situation in this test case - the user is trying to control the order of volatile accesses with an if statement.

      Compiler mistakenly reorders and combines conditional definitions of volatile objects

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            TI User
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            TI User
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                Connection: Intermediate to External PROD System
                EXTSYNC-2080 - Compiler mistakenly reorders and co...
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