This fix provides additional synchronization between the application CPU and the network processor (NWP) CPU, to avoid a potential problem when the network processor is aligning DCDC clocks, and the application CPU is simultaneously entering or exiting from low power deep sleep (LPDS). The Power driver on the application CPU now asserts a flag at the start of an LPDS transition, and releases it upon wake from LDPS; the NWP will monitor this flag and will not perform DCDC clock alignment during this interval.