There is a race condition in startTDC().AUX_SYSIFTDCREFCLKCTL.REQ is set and we should be waiting for the ACK bit to go high. Instead, the logic waits for it to go low. Since it starts low already and the logic runs on SCLKMF, that bit does not update until 0.5us after the first register write on PG1.1 HW. On FPGA, the ACK bit seems to update before the next instruction executes. That means that the faulty logic then tries to wait for the bit to go low, which it never will. The issue can be reliably reproduced on PG1.1 HW by adding a CPUdelay() between setting the REQ bit and the while loop.