The compiler will mistakenly define and use a register that is defined by a preceeding multi-cycle instruction while the definition of the value created by the multi-cycle instruction is still in the process of being written to that register. If an interrupt occurs between the delay slot definition of that register and the delay slot use of that register, then an incorrect value will arrive in the register for the delay slot use of the register. For example,          MPYLI .M1X A4,B6,A5:A4          MVK .S1 2380,A3   || ADD .L1X A3,B8,A5          ADD .L1 A3,A5,A9          LDHU .D1T1 *A9,A5          NOP 1          ... In the above code, if an interrupt occurs in the delay slots of the MPYLI instruction, between the definition of A5 and the subsequent use of A5, then the value in A5 used by the second ADD instruction will be the value that was written to A5 by the MPYLI instruction instead of the first ADD instruction.