Assembler does not encode the proper offset for a VLDR immediate instruction in thumb 2 mode

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    • Type: Bug
    • Resolution: Fixed
    • Priority: Medium
    • Code Generation Tools
    • CODEGEN-246
    • SDSCM00037308
    • ARM_4.7.0B1
    • ARM_5.0.0B1
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      The compiler will not generate this instruction. If the instruction is being used in an assembly routine, then it should be compiled in ARM mode. The instruction can be replaced with the following instruction sequence to get the correct results:
      ADR R0, mysym
      VLDR D0, [R0, #0]
      Show
      The compiler will not generate this instruction. If the instruction is being used in an assembly routine, then it should be compiled in ARM mode. The instruction can be replaced with the following instruction sequence to get the correct results: ADR R0, mysym VLDR D0, [R0, #0]

      Assembler does not encode the proper offset for a VLDR immediate instruction in thumb 2 mode

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            TI User
            Reporter:
            TI User
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              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-345 - Assembler does not encode the prope...
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