TI MCU NNC applies padding optimizations to certain operators (qnn.conv2d, nn.maxpool2d) with NHWC data layout so that these operators can be effectively mapped to TI NPU or TI M33 CDE.

A bug happens when this optimization was accidently applied to the operators with NCHW data layout. The fix is tighten the condition when this optimization can be applied. The bug exists in ti_mcu_nnc 2.1.0.LTS release, and will be fixed in 2.1.1.LTS patch release.

Typical behavior of the bug

The ti_mcu_nnc compiler will emit the following errors:

File "<tvm_install_path>/relay/backend/contrib/tinie/prepare.py", line 109, in QuantizeTINIEModel
    mod = relay.transform.InferType()(mod)
Error: The Relay type checker is unable to show the following types match:
  Tensor[(4, 384), int8]
  Tensor[(4, 640), int8]
In particular:
  dimension 1 conflicts: 384 does not match 640.

OR:

InternalError: Check failed: *axis_ptr == 1 (5 vs. 1) : cannot squeeze axis with dimension not equal to 1

Typical use cases that could trigger this bug

When a user compiles a quantized model not quantized by TI-NPU QAT for TI-NPU or M33 CDE.