In the 2.1.0.STS release, any delayed branch whose 3 subsequent instructions span more than 1 fetch packet (16 bytes) will cause a hardware fault due to an invalid encoding in the branch opcode.

BD @address
NOP || PAD || PAD || PAD || PAD || PAD || PAD || PAD || PAD
NOP || PAD || PAD || PAD || PAD || PAD || PAD || PAD || PAD
NOP || PAD || PAD || PAD || PAD || PAD || PAD || PAD || PAD
NOP || PAD || PAD || PAD || PAD || PAD || PAD || PAD || PAD

Above requires a full fetch of 3 16-byte packets. When affected by CODEGEN-15021, the 'BD' instruction will be encoded such that it will only fetch one, resulting in a hardware fault.

This issue is most easily recognized via hardware faults which occur at the point of the delayed branch, but can be confirmed through manual inspection of the size of the subsequent 3 instructions in addition to the value of the 2-bit encoded field which configures how many fetch packets are needed.

There is no workaround besides compiling with optimization level -O1, which suppresses the generation of delayed branches.