MMCSD: PHY DLL frequency is setting incorrectly for any clock < 200MHz

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    • Type: Bug
    • Resolution: Fixed
    • Priority: Medium
    • Linux Core SDK
    • LCPD-45700
    • 11.02
    • 12.00.00
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      am62pxx_sk-fs
      am64xx-hsevm
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      am62pxx_sk-fs am64xx-hsevm

      In host controller driver, when configuring the DLL, DLL FRQSEL is configured incorrectly for any clock < 200MHz. Fixup sdhci_am654_settup_dll to account for any frequency besides 200MHz in PHY CTRL 5 Reg.

      Fixes:
      PENDING: mmc: sdhci_am654: AM62: Limit DDR52 mode to 40MHz
      PENDING: mmc: sdhci_am654: Fix DLL FRQSEL
      PENDING: mmc: sdhci_am654: Enable DLL based on mmc->actual_clock
      PENDING: mmc: sdhci_am654: Allow defaults for DLL properties
      PENDING: mmc: sdhci_am654: Add SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN quirk
      PENDING: arm64: dts: ti: k3-am62a-main: Enable MMC DDR52
      PENDING: arm64: dts: ti: k3-am62l-main: Enable MMC DDR52
      –
      https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/log/?h=ti-linux-6.18.y

            Assignee:
            TI User
            Reporter:
            TI User
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              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-6343 - MMCSD: PHY DLL frequency is setting...
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