The VTM module design uses synchronizers to cross from the sensor clock to the VTM‑control and MMR (vbusp) clocks. Because the sensor runs much slower than the MMR side, back‑to‑back writes can be missed or sampled incorrectly, leading to nondeterministic behavior that is hard to reproduce on silicon.

VTM design specifications recommends at least a 1 µs inter‑write delay to ensure that the sensor reliably latches each configuration change, eliminating potential clock domain crossing issues

Inserting a ~1 µs delay after each register write performed in during initialization / sensor reset gives the sensor's 1 MHz clock domain enough time to capture the write before the next one arrives, preventing clock domain crossing related issues.