A Multi-Node Graph Stalls Completely Due to a Node Submitting a Process Request to an IP which is already Stalled due to a Previous Node

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    • Type: Bug
    • Resolution: Fixed
    • Priority: Urgent
    • Imaging System Software
    • ISS-1218
    • PSDK_11.0
    • psdk_11.2
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      We have identified a bug in the Watchdog Timer ISR where the error‑interrupt status bits for DOF and SDE are read incorrectly. As a result, the system may fail to detect fault conditions, allowing genuine failures to go unnoticed and preventing the automatic recovery action (reset or interrupt) that the watchdog is intended to perform. This issue does not affect other functionality, but it can leave the device in an unrecovered error state until a manual reset is performed.

      Workaround/Fix:

      The official fix for this bug is targeted for 11.2 PSDK release. The below fix can be applied in the code base.

      1. /src/drv/vhwa_m2mDofIntr.c
      @@ -615,10 +615,10 @@ static void vhwaM2mDofGetIntrStat(const Vhwa_M2mDofInstObj *instObj,
      &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][0U], errStat);

      vhwa_GetWdtimerErrIntrStat(&intdRegs->STATUS_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U],

      • &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U], wdTimer_errStat, 1);
        + &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U], wdTimer_errStat, 0);

      vhwa_GetWdtimerErrIntrStat(&intdRegs->STATUS_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U],

      • &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U], foco_wdTimer_errStat, 3);
        + &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U], foco_wdTimer_errStat, 2);
        regVal = CSL_REG32_RD(
        &intdRegs->STATUS_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][1U]);
        2. /src/drv/vhwa_m2mSdeIntr.c
        @@ -626,10 +626,10 @@ static void vhwaM2mSdeGetIntrStat(const Vhwa_M2mSdeInstObj *instObj,
        &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][0U], errStat);
      • &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U], wdTimer_errStat, 0);
        + &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U], wdTimer_errStat, 1);

      vhwa_GetWdtimerErrIntrStat(&intdRegs->STATUS_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U],

      • &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U], foco_wdTimer_errStat, 2);
        + &intdRegs->STATUS_CLR_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][2U], foco_wdTimer_errStat, 3);

      regVal = CSL_REG32_RD(
      &intdRegs->STATUS_REG_LEVEL_DMPAC_OUT[vhwaIrqNum][1U]);

            Assignee:
            TI User
            Reporter:
            TI User
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            Watchers:
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              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-6026 - A Multi-Node Graph Stalls Completel...
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