No masking for Relevant Bit Fields While Reading the Error Status Register in the vhwa_GetIntrStat() API

XMLWordPrintable

    • Type: Bug
    • Resolution: Fixed
    • Priority: Medium
    • PDK
    • PDK-18694
    • PROCESSOR_SDK_11.01.00
    • processor_sdk_11.01.01
    • Hide
      j721s2-hsfs-evm
      j742s2-hsfs-evm
      j784s4-hsfs-evm
      Show
      j721s2-hsfs-evm j742s2-hsfs-evm j784s4-hsfs-evm

      A bug was discovered in the vhwa_GetErrIntrStat call defined for all IPs, which does not take the relevant bit mask for the interrupts of the calling IP as an argument. Therefore, the whole 32-bit register, regardless of whether there are other bit fields in it, is returned as the error status.
      This can lead to erroneous error status for:
      1. NF and MSC

      2. DOF and SDE

       

      In our current implementation, we use separate IRQ lines and correspondingly separate INTD register instances for each IP, the bug is not expected to result in erroneous application behaviour. 

            Assignee:
            TI User
            Reporter:
            TI User
            Votes:
            0 Vote for this issue
            Watchers:
            2 Start watching this issue

              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-6016 - No masking for Relevant Bit Fields ...
                SYNCHRONIZED
                • Last Sync Date: