C28 silicon bug workaround: FastIntDiv or DIVF64 instruction preceded by certain FPU 2p operations

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    • Type: Bug
    • Resolution: Fixed
    • Priority: High
    • Code Generation Tools
    • CODEGEN-14240
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      Disable fastIntDiv and DIVF64 instructions with option: --idiv_support=none

      Lowering --opt_level can also potentially generate an instruction sequence that avoids the issue while still using above instructions, however, you must then check final assembly to ensure that any FastIntDiv or DIVF64 sequences do not have the previous 2 instructions as: MPYF32 ADDF32 SUBF32 MACF32 or parallel cases.
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      Disable fastIntDiv and DIVF64 instructions with option: --idiv_support=none Lowering --opt_level can also potentially generate an instruction sequence that avoids the issue while still using above instructions, however, you must then check final assembly to ensure that any FastIntDiv or DIVF64 sequences do not have the previous 2 instructions as: MPYF32 ADDF32 SUBF32 MACF32 or parallel cases.

      Certain 2p FPU instructions (listed below) need an additional delay slot prior to any fast integer division (idiv0) instructions and floating point accelerator (divf64) instructions. This is independent of any particular FPU register.

      NOTE: fastIntDiv and DIVF64 instructions require --idiv_support=idiv0 which can be disabled with --idiv_support=none
       
      For example, in below sequence, the ADDF32 instruction's R0H register value will leak into the R1H register after executing the ABSI32DIV32 instruction:
         ADDF32 R0H,R0H,#32768
         NOP     ; current single delay slot required by all 2p FPU instrs
         ABSI32DIV32 R2H,R1H,R3H
       
      Above issue is avoided by adding an additional delay slot.
       
      As part of this workaround, the compiler will be updated to generate code with two delay slots, and the assembler will be updated to check for the issue. 
       
      Below 2p FPU instructions are involved:
          ADDF32, ADDF32 || MOV32
          SUBF32, SUBF32 || MOV32
          MPYF32, MPYF32 || MOV32, MPYF32 || ADDF32, MPYF32 || SUBF32
          MACF32, MACF32 || MOV32
       
      Below idiv0 instructions are impacted:
          ABSI32DIV32 ABSI32DIV32U ABSI64DIV32 ABSI64DIV32U ABSI64DIV64 ABSI64DIV64U
          ENEGI32DIV32 ENEGI64DIV32 ENEGI64DIV64 MNEGI32DIV32 MNEGI64DIV32
          MNEGI64DIV32 MNEGI64DIV32 MNEGI64DIV32 MNEGI64DIV32 MNEGI64DIV32
          MNEGI64DIV64 NEGI32DIV32 NEGI64DIV32 NEGI64DIV64 SUBC2UI64 SUBC4UI32
      And below divf64 instructions are impacted:
          PREDIVF64 SUBC3F64 POSTDIVF64

      See below latest silicon errata for more details:
      TMS320F28P65x https://www.ti.com/lit/er/sprz545e/sprz545e.pdf
      TMS320F28002x https://www.ti.com/lit/er/sprz466d/sprz466d.pdf
      TMS320F28003x https://www.ti.com/lit/er/sprz496e/sprz496e.pdf
      TMS320F2838x https://www.ti.com/lit/er/sprz458g/sprz458g.pdf 

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            TI User
            Reporter:
            TI User
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