The R5 SPL only needs to run on Core0 on K3 SoCs, and commit ccdb7c2255bd ("armv7r: K3: Allow SPL to run only on core 0") already parks the CPU1 core on MCU R5 in WFI appropriately if the MCU R5FSS is booted in Split-mode by chance.

The release_resources_for_core_shutdown() function in am6_init.c & j721e_init.c has logic to shut down the R5F cores on both AM65x and J721E SoCs if no application is being booted on the R5. However, the current logic shuts down the cores in a fixed Core1 followed by Core0 sequence. The function doesn't check for the LockStep/Split-mode status, as the order of cores to be shutdown is different in both modes.

Fix details:
https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/?h=ti-linux-6.12.y&id=141dc8410ea2828f00a851e557f1f903293a44c1