Under --opt_level=0, code generated by the compiler misuses upper half of register pair, leading to incorrect computation

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    • Type: Bug
    • Resolution: Cannot Reproduce
    • Priority: Medium

      The attached test case has these lines ...

      	unsigned long int sec_start;
      	/* ... */
      	sec_start = global_sec_count;
      	while((global_sec_count - sec_start) <= 3)// wait 3 seconds
      	{
      		__no_operation();
      		__delay_cycles(  ((unsigned long int) 2000000) * 1
      		               / ((unsigned long int) 1));
      		__no_operation();
      	}
      

      Build it ...

      % cl430 -@options.txt file.c
      "file.c", line 1847: remark #1528-D: (ULP 3.1) Detected flag polling using SFRIFG1. Recommend using an interrupt combined with enter LPMx and ISR
      "file.c", line 1886: remark #1527-D: (ULP 2.1) Detected SW delay loop using __delay_cycles. Recommend using a timer module instead
      

      Ignore the diagnostics. Inspect the assembly code in file.asm. Note the use of the register r13 in the last function.

      The register pair r13:r12 is allocated to the local 32-bit variable sec_start. It is initialized before the start of the while loop. Inside the while loop, the register r13 is used to implement the __delay_cycles intrinsic. Then the register pair r13:r12 is compared to 3 to see whether the while loop continues. That doesn't work, because r13 now holds an unrelated value.

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            TI User
            Reporter:
            TI User
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              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-5776 - Under --opt_level=0, code generated...
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