Description:
In TX_RX_Mode ,inside Spi_DmaRxIsrHandler Spi_processChCompletion is called which in return disables all the interrupts of Tx, Rx and clears FIFO for read ,write etc...

If we consider getting Rx interrupt first then in Spi_DmaRxIsrHandler we clear all the interrupts of Tx, Rx etc.. without serving Tx interrupt .This creates an issues if Tx interrupt is followed by Rx interrupt.

Inside SPI Dma handlers we need to check the other interrupt status occurence.

 if ((MCSPI_TX_EDMA_CALLBACK_OCCURED == chObj->dmaCbCheck) ||
            (MCSPI_RX_ONLY_MODE == chnCfg->trMode))
        {
            /* Now Both Tx and Rx EDMA Callbacks have happened */
            chObj->dmaCbCheck = 0x0U;

            /* Clear error status */
            intStatus = McSPIChannelStatusGet(hwAttrs->baseAddr, chNum);
            MCSPI_clearIntErrStatus(mcHandle, intStatus);

            /* Call the completion function */
            MCSPI_dmaCompleteIOCallback(mcHandle);
        }

The feasibilty to modify both Spi_DmaTxIsrHandler and Spi_DmaTxIsrHandler in MCAL SPI driver.

Resolution:
Disable intr only in Tx/Rx ISRcall whichever comes later
Root Cause:
DmaRxHandler calls Spi_processChCompletion which disables both Tx ,Rx interrupts