USB2 PHY locks up due to short suspend

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    • Type: Bug
    • Resolution: Fixed
    • Priority: Medium
    • Linux Core SDK
    • LCPD-37352
    • 09.00.00
    • 09.02.00
    • am64xx-evm
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      The workaround will ensure that the faulty logic is bypassed and hence lockup will be avoided.

      Workaround for AM62, AM62A, AM62P:
      The following register fields have to be written during USB initialization (after LPSC removes USB reset but before USB Controller initialization) to avoid this lockup. Both bits can be written at the same time or alternatively bit 5 can be set before bit 4. <bold>It has to be ensured that bit 4 is NOT set before bit 5.<\bold>
      Set PLL_REG12.pll_ldo_ref_en field (bit 5) in PHY2 region to 1
      Set PLL_REG12.pll_ldo_ref_en_en field (bit 4) in PHY2 region to 1

      This workaround only bypasses the faulty logic and does NOT prevent the faulty logic from locking up. As a result, this workaround needs to be set during USB initialization and should remain active throughout USB operation.

      Workaround for AM64x, J7ES, J7VCL, J7AEP, J7AMP, J7AHP, J7AEN:
      Set SUSP_CTRL register suspend_residency_enable field to 1 during Controller initialization (post-ROM). This register is at offset 0x48 in USB 3.0 Controller register space. It can be set to 1 during initialization and can be retained at this value throughout operation.
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      The workaround will ensure that the faulty logic is bypassed and hence lockup will be avoided. Workaround for AM62, AM62A, AM62P: The following register fields have to be written during USB initialization (after LPSC removes USB reset but before USB Controller initialization) to avoid this lockup. Both bits can be written at the same time or alternatively bit 5 can be set before bit 4. <bold>It has to be ensured that bit 4 is NOT set before bit 5.<\bold> Set PLL_REG12.pll_ldo_ref_en field (bit 5) in PHY2 region to 1 Set PLL_REG12.pll_ldo_ref_en_en field (bit 4) in PHY2 region to 1 This workaround only bypasses the faulty logic and does NOT prevent the faulty logic from locking up. As a result, this workaround needs to be set during USB initialization and should remain active throughout USB operation. Workaround for AM64x, J7ES, J7VCL, J7AEP, J7AMP, J7AHP, J7AEN: Set SUSP_CTRL register suspend_residency_enable field to 1 during Controller initialization (post-ROM). This register is at offset 0x48 in USB 3.0 Controller register space. It can be set to 1 during initialization and can be retained at this value throughout operation.

      USB 2.0 PHY locks up due to short suspend. PHY stops providing UTMI clock after waking up from suspend if the wakeup occurs within 3us after entering suspend. The USB 2.0 link wakeup event can occur during PHY suspend entry and cause this corner case to be triggered.

      Once lockup occurs, it can only be recovered by power cycling (warm reset is ineffective). However, the below workaround will ensure that the faulty logic is bypassed and hence lockup can be avoided.
       
      Workaround
      Set SUSP_CTRL register suspend_residency_enable field to 1 during Controller initialization (post-ROM). This register is at offset 0x48 in USB 3.0 Controller register space. It can be set to 1 during initialization and can be retained at this value throughout operation. ROM update is NOT needed since ROM does not suspend USB.

            Assignee:
            TI User
            Reporter:
            TI User
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              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-5052 - USB2 PHY locks up due to short suspend
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