There's GPMC-NAND timing parameter configurations in u-boot DTS board file
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/dts/am335x-evm.dts?h=09.02.00.003#n497

But apparently GPMC parameter timing in u-boot DTS board file is NOT currently used in SPL/u-boot.

Here is the SPL call flow on configuring GPMC_CONFIG1_0 through GPMC_CONFIG7_0 registers with JTAG [1] [2]
[1] am3_9.1_spl_gpmc_init_call_flow.docx
[2] am3_9.1_spl_gpmc_init_call_flow.log

Instead GPMC parameters are configured in u-boot source code. Here is the dump of GPMC_CONFIG1_0 through GPMC_CONFIG7_0 @u-boot
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/include/asm/arch-am33xx/mem.h?h=09.02.00.003#n40

[3] am3_9.1.0.1_gpmc_rd.log: the current GPMC timing parameter configuration and nand read performance @u-boot.

The "testing patch" to overwrite the hardcoded GPMC_CONFIG1_0 through GPMC_CONFIG7_0 with the new values based on Linux device tree:
the u-boot testing patch
[4] 0001-GPMC-NAND-register-timing-in-SPL-for-the-NAND-on-AM3.patch

The updated GPMC timing parameter configuration and nand read performance @u-boot
[5] am3_9.1.0.1_patch_gpmc_rd.log

NAND read time is improved x4 on reading 8Mbytes @u-boot with the updated GPMC timing parameter

• 1.85Mbyte/s with the current hardcoded GPMC parameter timing
• 7.7Mbyte/s with the updated GPMC parameter timing