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Bug
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Resolution: Unresolved
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Medium
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Code Generation Tools
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CODEGEN-12367
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ARMCLANG_3.2.0.LTS
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ARMCLANG_3.2.3.LTS*
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default
The attached file has these lines ...
#include <stdatomic.h>
extern atomic_flag flag;
void test()
{
atomic_flag_test_and_set_explicit(&flag, memory_order_acquire);
}
Build it. Then disassemble.
% tiarmclang -mcpu=cortex-r5 -O3 -c file.c % tiarmdis file.o Disassembly of file.o: TEXT Section .text.test, 0x28 bytes at 0x00000000 000000: test: 000000: .arm 000000: 001000E3 MOVW R1, #0 000004: 0100A0E3 MOV R0, #1 000008: 001040E3 MOVT R1, #0 00000c: 00F020E3 MSR CPSR_, #0 000010: 9F2FD1E1 LDREXB R2, [R1] 000014: 902FC1E1 STREXB R2, R0, [R1] 000018: 000052E3 CMP R2, #0 00001c: FBFFFF1A BNE 0x00000010 000020: 5BF07FF5 PLD 0xFFFFFFCD 000024: 1EFF2FE1 BX R14
The MSR and PLD instructions are wrong. Compare that to the correct output of tiarmobjdump -d ...
% tiarmobjdump -d file.o
file.o: file format elf32-littlearm
Disassembly of section .text.test:
00000000 <test>:
0: e3001000 movw r1, #0
4: e3a00001 mov r0, #1
8: e3401000 movt r1, #0
c: e320f000 nop
10: e1d12f9f ldrexb r2, [r1]
14: e1c12f90 strexb r2, r0, [r1]
18: e3520000 cmp r2, #0
1c: 1afffffb bne 0x10 <test+0x10> @ imm = #-20
20: f57ff05b dmb ish
24: e12fff1e bx lr
