Enet LLD provides bit-banging based approach to read and write PHY registers (clause-22) where MDIO is put in manual mode and the driver manipulates the MDIO data and clock signals. This approach is needed for i2329 errata (see https://www.ti.com/lit/er/sprz455d/sprz455d.pdf)

However, the Enet LLD implementation is missing the MDIO preamble which consists of 32 ones sent before START field. This can break compatibility with Ethernet PHYs that don't support preamble suppression.

PHY in TI EVMs do support preamble suppression, so this issue is not observed on any of Jacinto EVMs.