J7200: GPIO setting to 1 for VPP fails on the Socketed SoM

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    • Type: Bug
    • Resolution: Fixed
    • Priority: Urgent
    • PDK
    • PDK-12735
    • PROCESSOR_SDK_08.06.00
    • PROCESSOR_SDK_09.00.00
    • j7200-evm

      Issue Description
      Couple of fixes needed for keywriter to be functional on J7200 Socketed SoM: PROC105E8A(003)

      (1)

      Keywriter software as part of PMIC initialization clears all the pending interrupts. One of the clears is causing a reset.

      The RTOS PMIC code reads the WD_ERR_STATUS register & reads 0xF1. It tries to clear it by writing the same & that triggers SOC reset.

      This was not the case on the J721e dual Leo SOM or the j7200 dual Leo SOM.

      (2)

      The Hera PMIC GPIO5 is driving the VPP Voltage so this should be OTP as output at reset.
      However on the latest revision of socketed SOM (PROC105E8A(003))the PMIC register for GPIO5 reads: 0x18Input.
      So VPP GPIO is input and hence setting HIGH is failing.

      This needs a software change to first change the direction to Output but OTP value is counter intuitive on the Socketed SOMPROC105E8A(003).

      Resolution
      (1) Masked clearing interrupts of PMIC such that a reset will not happen.
      (2) Added a new function to set the direction of GPIO to input in pmic_gpio.c

            Assignee:
            TI User
            Reporter:
            TI User
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              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-4094 - J7200: GPIO setting to 1 for VPP fa...
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