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Type:
Bug
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Resolution: Fixed
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Priority:
High
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PDK
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PDK-13073
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PROCESSOR_SDK_09.00.00
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PROCESSOR_SDK_09.00.00
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j7200-evm
Issue Description:
There is a significant increase in the time taken by MSMC tests
PDK-3485 Timing:
| SBL | APP | Time (Secs) |
|---|---|---|
| 9.0 | 9.0 | 47 |
| 8.6 | 9.0 | 20 |
| 9.0 | 8.6 | 20 |
| 8.6 | 8.6 | 20 |
Run 9.0 SBL and 9.0 app to observe significant increase in execution time of MSMC tests
Resolution Description:
TIFS 9.0 is setting MSMC clock to 307.2 MHz during tifs load and not re-initializing these MSMC PLLs to 1 GHz during PM init. The expected behavior is TIFS to set frequency to 1 GHz by default and not reprogram these PLLs during PM INIT. As a workaround set msmc clock to 1GHz in board_pll.c
