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  1. Embedded Software & Tools
  2. EXT_EP-11371

J784S4/J721S2: SBL fails to initialize DDR after warm reset

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    • Icon: Bug Bug
    • Resolution: Fixed
    • Icon: Urgent Urgent
    • PDK
    • PDK-12717
    • PROCESSOR_SDK_08.06.00
    • PROCESSOR_SDK_09.00.00
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      Issue Description:
      The SBL hangs during initialization when a warm reset is applied to the board. The issue is seen only with SBL. The Linux R5 SPL does not show the same behavior.

      Resolution Description:
      This is caused due to DDR1, DDR2, DDR3 registers are not unlocked by default and DDR PLL is not proper during warm reset.
      Now implemented proper unlocking mechanism in Board library for those registers.

            syncuser TI User
            syncuser TI User
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              Created:
              Updated:
              Resolved: