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  1. Embedded Software & Tools
  2. EXT_EP-11365

[SBL] SBL_DCacheClean does not writeback full cache contents


    • Icon: Bug Bug
    • Resolution: Fixed
    • Icon: High High
    • PDK
    • PDK-12823
    • PROCESSOR_SDK_08.06.00
    • PROCESSOR_SDK_09.00.00
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      j721s2-evm j784s4-evm

      Issue Description:
      Cache clean implementation for SBL seems to be broken. On cold boots, once MCU R5F loads ATF images to ram and release A72, sometimes atf/optee stays in exception. This was tracked down to place where relocation tables for optee are broken in DDR and correct in R5F cache. This code do flush of cache in SBL:

      void SBL_DCacheClean(void *addr, uint32_t size)
      uint32_t set = 0, way = 0;
      uint32_t cacheLineSize = CSL_armR5CacheGetDcacheLineSize();
      uintptr_t firstAddr = (uintptr_t ) addr & ~(cacheLineSize -1U);
      uintptr_t lastAddr = (uintptr_t) addr + size;
      uintptr_t num_iterations = (lastAddr - firstAddr) / cacheLineSize;

      if (num_iterations < 64 * 4)

      { /* Invalidate by MVA */ CSL_armR5CacheWbInv((const void *)addr, uint32_to_int32(size)); }

      /* Invalidating full cache by set and way is more efficient */
      for (set = 0; set < 128; set ++)
      for (way = 0; way < 4; way++)

      { CSL_armR5CacheCleanInvalidateDcacheSetWay(set, way); }



      When "CSL_armR5CacheCleanInvalidateDcacheSetWay" is executed at runtime, not whole memory is flushed and some parts stays in R5F cache. If we modify code to always do "CSL_armR5CacheWbInv" everything works correct.

      Used CSL API's to get the number of sets and number of ways for different SOC's to perform SBL_DCacheClean().
      Earlier number of sets and number of ways were hard coded in the SBL driver.

            syncuser TI User
            syncuser TI User
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