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Bug
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Resolution: Fixed
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Medium
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PDK
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PDK-12880
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PROCESSOR_SDK_08.05.00
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PROCESSOR_SDK_09.00.00
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Issue Description:
PDK driver enables the PHY pipeline only when either DMA is enabled and/or cache is enabled. Please refer to the OSPI_dac_xfer_mode_read_v0 API in OSPI_v0.c
#ifdef SPI_DMA_ENABLE if (hwAttrs->dmaEnable == (bool)true) { if (hwAttrs->phyEnable == (bool)true) { /* Enable PHY pipeline mode for read */ CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE); } OSPI_dmaTransfer(handle, transaction); } else #endif { if (hwAttrs->cacheEnable == (bool)true) { if (hwAttrs->phyEnable == (bool)true) { /* Enable PHY pipeline mode for read */ CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE); } }
Ideally we should be able to use the PHY pipeline with PHY mode enabled without any dependency on Cache or DMA. Could not find any documentation that explains any such restriction
Also, trying on enable the pipeline when DMA and cache are not enabled leads to data mismatch errors.
Resolution Description:
PHY Pipeline requires to read at least four AHB 4-byte-sized words (16 bytes) in a sequential manner. Hence PHY is supported only when either DMA or Cache is enabled in the system. Updated OSPI documentation for the same