Issue Description:

On J721E, SBL unconditionally overrides DRVSTRNGTH field in PADCONF registers in sbl_soc.c. Please refer to the below code:

By writing 0xD, 0xD, 0xD … SBL overrides the die to die adjustments that may be done on ATE resulting in nom/fast/slow having the exact same behavior.

static void J721E_SetupLvCmosDriveStrength(void)
{
    volatile uint32_t *reg1 = (uint32_t *)0x43005008;
    volatile uint32_t *reg2 = (uint32_t *)0x4300500C;
    volatile uint32_t *lvcmos_drv_h_base = (uint32_t *)0x430060c0;
    volatile uint32_t *lvcmos_drv_v_base = (uint32_t *)0x430060d0;
    volatile uint32_t i;

    *reg1 = 0x68EF3490;
    *reg2 = 0xD172BC5A;

    /* Workaround for fixing lvcmos drive strength */
    for (i = 0; i < 4; i++)
    {        *(lvcmos_drv_h_base + i) = 0xD;        *(lvcmos_drv_v_base + i ) = 0xD;     }
}

Resolution Description:

Drive strength field in PAD config register should be set as specified by efuse. Early silicon samples did not have full efuse programming, so SBL was programming 0xD as a workaround.
Removed workaround from SBL