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  1. Embedded Software & Tools
  2. EXT_EP-11064

K3conf wrong frequencies

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    • Icon: Bug Bug
    • Resolution: Fixed
    • Icon: Medium Medium
    • Linux Core SDK
    • LCPD-28645
    • Unknown
    • 09.00.00
    • j721e-idk-gw

      K3CONF                 (version v0.1-34-g1ff0c4f built Mon Jan 25 03:49:57 UTC 2021)

       SoC        J721E SR2.0                                                  

       SYSFW                  ABI: 3.1 (firmware version 0x0014 ')')                       

      Interrogating the processors gives the following table in which it looks like all processor frequencies are mis-aligned:

      Device ID  Processor ID  Processor Name    Processor State  Processor Frequency
      202 32 A72SS0_CORE0     DEVICE_STATE_ON 3.26E+18
      203 33 A72SS0_CORE1     DEVICE_STATE_ON 2E+09
      142 3 C66SS0_CORE0     DEVICE_STATE_ON 2E+09
      143 4 C66SS1_CORE0     DEVICE_STATE_ON 1.35E+09
      15 48 C71SS0           DEVICE_STATE_ON 1.35E+09
      250 1 MCU_R5FSS0_CORE0 DEVICE_STATE_ON 1E+09
      251 2 MCU_R5FSS0_CORE1 DEVICE_STATE_ON 1E+09
      245 6 R5FSS0_CORE0     DEVICE_STATE_ON 1E+09
      246 7 R5FSS0_CORE1     DEVICE_STATE_ON 1E+09
      247 8 R5FSS1_CORE0     DEVICE_STATE_ON 1E+09
      248 9 R5FSS1_CORE1     DEVICE_STATE_ON 1E+09

       

      Looking at the clocks, A72 makes sense (but differ from the processors dump); C7x may make sense; the R5F clocks do not make sense (ID 245 and 246 clocks should be identical, but Clock ID 0 is not…) :

      Device ID  Clock ID  Clock Name                                                                       Status               Clock Frequency    
      15 0 DEV_C71SS0_C7X_CLK                                                               CLK_STATE_READY     1.25E+08
      15 1 DEV_C71SS0_PLL_CTRL_CLK                                                          CLK_STATE_READY     1E+09
               
      202 2 DEV_A72SS0_CORE0_ARM_CLK_CLK                                                     CLK_STATE_READY     2E+09
      203 0 DEV_A72SS0_CORE1_ARM_CLK_CLK                                                      CLK_STATE_READY     2E+09
               
      245 0 DEV_R5FSS0_CORE0_CPU_CLK                                                          CLK_STATE_READY     1.25E+08
      245 1 DEV_R5FSS0_CORE0_INTERFACE_CLK                                                   CLK_STATE_READY     1E+09
      245 2 DEV_R5FSS0_CORE0_INTERFACE_PHASE                                                  CLK_STATE_READY     1E+09
      246 0 DEV_R5FSS0_CORE1_CPU_CLK                                                         CLK_STATE_READY     1E+09
      246 1 DEV_R5FSS0_CORE1_INTERFACE_CLK                                                   CLK_STATE_READY     1E+09
      246 2 DEV_R5FSS0_CORE1_INTERFACE_PHASE                                                 CLK_STATE_READY     1E+09
      247 0 DEV_R5FSS1_CORE0_CPU_CLK                                                         CLK_STATE_READY     1.25E+08
      247 1 DEV_R5FSS1_CORE0_INTERFACE_CLK                                                   CLK_STATE_READY     1E+09
      247 2 DEV_R5FSS1_CORE0_INTERFACE_PHASE                                                 CLK_STATE_READY     1E+09
      248 0 DEV_R5FSS1_CORE1_CPU_CLK                                                         CLK_STATE_READY     1E+09
      248 1 DEV_R5FSS1_CORE1_INTERFACE_CLK                                                   CLK_STATE_READY     1E+09
      248 2 DEV_R5FSS1_CORE1_INTERFACE_PHASE                                                 CLK_STATE_READY     1E+09

            syncuser TI User
            syncuser TI User
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              Created:
              Updated:
              Resolved: