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Bug
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Resolution: Fixed
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High
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PDK
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PDK-12406
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unknown
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PROCESSOR_SDK_08.02.00
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PROCESSOR_SDK_08.06.00
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- PV variance is associated with the OSPI PHY DLL delay elements on J7 devices
- When the 128 DLL delay elements are shorter than an OSPI Clock Cycle this will result in the Master delay line failing to lock on a Full Clock Cycle, and automatically locking in Half Cycle mode (DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD = 2)
- The OSPI PHY tuning algorithm (nor_spi_phy_tune.c) is is currently hard-coded to search the range of 0-63 RxDLL and TxDLL delay elements. This is correct when a full-cycle DLL lock is achieved in DTR mode.
- When DTR mode + Half Clock Cycle lock mode is enabled the OSPI PHY tuning algorithm (nor_spi_phy_tune.c) should be searching the range of 0-127 RxDLL/TxDLL delay elements, however it is not.
- DDR Mode: Master mode should be used for all frequencies > 1/(2*128*40ps), which works out to 97.7MHz. We should probably round up to the nearest achievable/customary frequency to give some margin to the 40ps min delay element design simulation result.
- SDR Mode: Master mode should be used for all frequencies > 1/(128*40ps), which works out to 195.4MHz. We should probably round up to 200MHz. However, I think the max SDR frequency supported in the datasheets is currently 166MHz, so Bypass Mode may always be required for SDR Mode.
- DDR Mode: Force Half-cycle DLL lock mode in all cases, since a full-cycle lock is not guaranteed <195.4MHz
- SDR Mode: Likely N/A per above bullets
- Search Window narrowing macros shall not be configured by default in nor_spi_phy_tune.h to minimize PHY tuning algorithm search range.
