Uploaded image for project: 'Embedded Software & Tools'
  1. Embedded Software & Tools
  2. EXT_EP-10960

[CSL-R5F] Incorrect usage of DMB and DSB for cache operations

XMLWordPrintable

    • Icon: Bug Bug
    • Resolution: Fixed
    • Icon: High High
    • PDK
    • PDK-12218
    • Huawei
    • PROCESSOR_SDK_08.04.00
    • PROCESSOR_SDK_08.05.00
    • Hide
      j721e-evm
      j7200-evm
      j721e-hsevm
      j721s2-evm
      j7200-hsevm
      j784s4-evm
      j721s2-hsevm
      j784s4-hsevm
      Show
      j721e-evm j7200-evm j721e-hsevm j721s2-evm j7200-hsevm j784s4-evm j721s2-hsevm j784s4-hsevm

      R5F code uses CacheP_wb/CacheP_Inv/CacheP_wbInv APIs for cache operation on R5F. This API internally uses CSL_armR5CacheWb/CSL_armR5CacheWbInv/CSL_armR5CacheInv CSL APIs for the cache operations. The CSL APIs internally runs a loop to writeback/invalidate cache. But for each loop, the CSL ASM implementation calls DMB/DSB instructions on everytime. This should not be called everytime, as it affects R5F performance.. 

            syncuser TI User
            syncuser TI User
            Votes:
            0 Vote for this issue
            Watchers:
            2 Start watching this issue

              Created:
              Updated:
              Resolved: