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Type: Bug
Resolution: Fixed
Priority: Medium

Product:
PDK
Internal ID:
PDK-12164
Forum URL:
EXTSYNC-3513
Found In Release:
PROCESSOR_SDK_08.02.00
Fix In Release:
PROCESSOR_SDK_08.05.00
Affected Platform/Device:

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j721e-evm
j7200-evm
j721s2-evm
j784s4-evm

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j721e-evm j7200-evm j721s2-evm j784s4-evm

DDR end Address given in below macro in Board is incorrect, when ECC is enabled.
#define BOARD_DDR_ECC_END_ADDR (0xF1FFFFFFU)

It should be set to (0xF1C71C71), instead of (0xF1FFFFFFU).

Assignee:: TI User
Reporter:: TI User
Votes:: 0 Vote for this issue
Watchers:: 2 Start watching this issue

Created:: 30/Aug/22 1:38 AM
Updated:: 12/Dec/22 8:10 AM
Resolved:: 12/Dec/22 8:10 AM

Connection: Intermediate to External PROD System

EXTSYNC-3513 - Incorrect DDR End Address with ECC ...
SYNCHRONIZED

Last Sync Date:

12/Dec/22 08:10 AM