After MCU only mode to Active mode switch for the SoC, passing the RM, PM, Sec and common board cfg does not enable PLL1 and PLL3.

PLL1 sources the UART FCLK and hence UART register access crashes the core.

This is needed for bringing back the full system after coming from a low power mode.

I am attaching:

1. PLL1_register_before_MCU_ONLY_ACTIVE_switch.bat (PLL1 registers in active mode before MCU only to Active mode switch)
2. PLL1_register_after_MCU_ONLY_ACTIVE_switch.bat (PLL1 registers in active mode after MCU only to Active mode switch)

Also attaching PLL0 registers for reference, there is no delta in the before and after version for PLL0.