Loading...

All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.

XML

Word

Printable

Type: Bug
Resolution: Fixed
Priority: Medium

Product:
PDK
Internal ID:
PDK-10131
Found In Release:
PROCESSOR_SDK_07.03.00
Fix In Release:
PROCESSOR_SDK_08.00.00
Affected Platform/Device:

Hide
j721e-evm
j7200-evm

Show
j721e-evm j7200-evm

In the Board_init, McSPI clock is configured for 50MHz.

{ TISCI_DEV_MCSPI0, TISCI_DEV_MCSPI0_CLKSPIREF_CLK, 50000000 }

, //MAIN_PLL0_HSDIV5_CLKOUT

but in McSPI example, inputClkFreq variable is used as 48MHz. Because of this mismatch, output clock rate is not matching.

Assignee:: TI User
Reporter:: TI User
Votes:: 0 Vote for this issue
Watchers:: 2 Start watching this issue

Created:: 15/Jul/21 11:58 AM
Updated:: 15/Jul/21 11:58 AM
Resolved:: 15/Jul/21 11:58 AM

Connection: Intermediate to External PROD System

EXTSYNC-3007 - [McSPI] Incorrect input clock in ex...
SYNCHRONIZED

Last Sync Date:

15/Jul/21 11:58 AM