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  1. Embedded Software & Tools
  2. EXT_EP-10414

[RTLS / CM] rtls_passive hop sequence may be wrong

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Details

    • Bug
    • Status: Fixed
    • Medium
    • Resolution: Fixed
    • SimpleLink CC13x2-26x2 SDK BLE5 Stack
    • BLE_AGAMA-3071
    • BLE Stack BLE5-2.1.5 RC1
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      BLE Stack BLE5-2.2.2 RC2
      BLE Stack BLE5-2.2.2
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      BLE Stack BLE5-2.2.2 RC2 BLE Stack BLE5-2.2.2

    Description

      SDK version: simplelink_cc13x2_26x2_sdk_4_40_00_44
      Project: rtls_passive
      Description: When the passive misses one connection event, it seems like not using the proper hop sequence. This leads it to lose track of the connection.

      Reproducibility: 100% when some packets are lost

      Steps to reproduce:

      1. Flash 3 boards with rtls_master, rtls_passive, rtls_slave (no modification required)
      2. Connect a logic analyzer to DIO2 and DIO3 of the rtls_master and rtls_passive
      3. Run the oob rtls_example_with_rtls_util.py python script - Start recording with the logic analyzer
      4. Interfere with the passive in order to have it losing some packets (I basically put my hand over it)

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            syncuser TI User
            syncuser TI User
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            Dates

              Created:
              Updated:
              Resolved: