MASTER _BYPASS bit in PHY_MASTER_CONTROL should be controlled based on the clock

XMLWordPrintable

    • Type: Bug
    • Resolution: Fixed
    • Priority: High
    • PDK
    • PDK-9433
    • PROCESSOR_SDK_07.02.00
    • PROCESSOR_SDK_08.00.00
    • j721e-evm

      MASTER_BYPASS bit is by default reset in the PDK OSPI driver. But this should be controlled based on the clock.
      It should be set for clock upto 166MHz and reset for clock exactly 166MHz.
      Without this fix, read can fail in DMA mode.

            Assignee:
            TI User
            Reporter:
            TI User
            Votes:
            0 Vote for this issue
            Watchers:
            2 Start watching this issue

              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-2839 - MASTER _BYPASS bit in PHY_MASTER_CO...
                SYNCHRONIZED
                • Last Sync Date: