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  1. Embedded Software & Tools
  2. EXT_EP-10315

MASTER _BYPASS bit in PHY_MASTER_CONTROL should be controlled based on the clock

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    • Icon: Bug Bug
    • Resolution: Fixed
    • Icon: High High
    • PDK
    • PDK-9433
    • PROCESSOR_SDK_07.02.00
    • PROCESSOR_SDK_08.00.00
    • j721e-evm

      MASTER_BYPASS bit is by default reset in the PDK OSPI driver. But this should be controlled based on the clock.
      It should be set for clock upto 166MHz and reset for clock exactly 166MHz.
      Without this fix, read can fail in DMA mode.

            syncuser TI User
            syncuser TI User
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