ICSS V1 CSL not up to date with ICSSG

The ICSS V1 CSL still has ICSSM limitations and not expanded for ICSSG. This needs to be updated.

Customer-flagged issue relates to the restriction on host interrupts. The CSL restricts the INTC to setting 10 host interrupts (0-9), which is the number available in ICSSM. ICSSG allows for 20 host interrupts.

Outside of the specific customer issue, the CSL should be checked to confirm ICSSG updates, including the additional RTU and TX_PRU are comprehended.

Likely the CSL files need to be moved to the V2 folder and updated there.

Customer report for INTC below:

At the moment I am evaluating the possibility of communication between ARM and ICSSG RTU (not to be confused with PRU).

 

On the ARM side, I would like to use PRUICSS_pruSendEvent to generate the ARM_RTU0_EVENT event which should be detected and handled by RTU.

 

According to the documentation ( TRM AM65x (SPRUID7D)  chapter  6.4.7.1 PRU_ICSSG Interrupt Controller Functional Description) to do this, I need to configure the INTC so that ARM_RTU0_EVENT is bound to HOST_INT_10 which in turn is connected to bit 30 of the register R31 of the RTU.

 

However, doing that I faced the following problem:

 

I do initialization of the Interrupt controller (INTC) of the ICSSG with a PRUICSS_pruIntcInit(pruIcssHandle, &pruss_intc_initdata) and my pruss_intc_initdata looks as following:

 

PRUICSS_IntcInitData pruss_intc_initdata = PRUSS_INTC_INITDATA;

 

#define ARM_PRU0_EVENT      16      //   pr0_pru_mst_intr[0]_intr_req   32

#define ARM_PRU1_EVENT      17      //   pr0_pru_mst_intr[1]_intr_req   33

…

#define ARM_RTU0_EVENT      26      //   pr0_pru_mst_intr[10]_intr_req  42

#define ARM_RTU1_EVENT      27      //   pr0_pru_mst_intr[11]_intr_req  43

 

#define CHANNEL0                0

#define CHANNEL1                1

…

#define CHANNEL10               10

#define CHANNEL11               11

 

 

#define PRU0                    0

#define PRU1                    1

…

#define RTU0                    10

#define RTU1                    11

 

#define PRU0_HOSTEN_MASK            0x0001

#define PRU1_HOSTEN_MASK            0x0002

…

#define RTU0_HOSTEN_MASK            0x0400

#define RTU1_HOSTEN_MASK            0x0800

 

#define SYS_EVT_POLARITY_LOW        0

#define SYS_EVT_POLARITY_HIGH       1

 

#define SYS_EVT_TYPE_PULSE          0

#define SYS_EVT_TYPE_EDGE           1

 

#define PRUSS_INTC_INITDATA

{   \ {   \     ARM_PRU0_EVENT,         \     ARM_PRU1_EVENT,         \     ARM_RTU0_EVENT,         \     ARM_RTU1_EVENT,         \     0xFF                    \ },  \ {   \     \{ARM_PRU0_EVENT,        CHANNEL0,   SYS_EVT_POLARITY_HIGH,  SYS_EVT_TYPE_PULSE}

,    \

    {ARM_PRU1_EVENT,        CHANNEL1,   SYS_EVT_POLARITY_HIGH,  SYS_EVT_TYPE_PULSE},    \

    {ARM_RTU0_EVENT,        CHANNEL10,  SYS_EVT_POLARITY_HIGH,  SYS_EVT_TYPE_PULSE},    \

    {ARM_RTU1_EVENT,        CHANNEL11,  SYS_EVT_POLARITY_HIGH,  SYS_EVT_TYPE_PULSE},    \

    {0xFF, 0xFF, 0xFF, 0xFF}   \

},  \

{   \     \{CHANNEL0,  PRU0}

,          \

    {CHANNEL1,  PRU1},          \

    {CHANNEL10, RTU0},          \

    {CHANNEL11, RTU1},          \

    {0xFF,0xFF}                 \

},  \

  ( PRU0_HOSTEN_MASK | PRU1_HOSTEN_MASK | RTU0_HOSTEN_MASK | RTU1_HOSTEN_MASK) \

}

After invoking PRUICSS_pruIntcInit (…) I see that the ICSSG_ENABLE_HINT_REG (Host Int Enable) register contains an incorrect value 0x00000*0*03 instead of 0x00000*C*03 (which is PRU0_HOSTEN_MASK|PRU1_HOSTEN_MASK|RTU0_HOSTEN_MASK|RTU1_HOSTEN_MASK= 0x00000*C*03).

 

With the Debugger I found the problem:

The register value ICSSG_ENABLE_HINT_REG is set in the C:\ti\pdk_am65xx_1_0_7\packages\ti\drv\pruss\src\pruicss_intc.c : Line 224

 

HW_WR_FIELD32((baseaddr  + CSL_ICSSINTC_HIER),CSL_ICSSINTC_HIER_ENABLE_HINT,prussintc_init_data->host_enable_bitmask);

 

which uses a macro:

 

#define HW_WR_FIELD32(regAddr, REG_FIELD, fieldVal)                            \

    (HW_WR_FIELD32_RAW((uint32_t) (regAddr), ((uint32_t)REG_FIELD##_MASK),                   \

                          ((uint32_t)REG_FIELD##_SHIFT), (uint32_t)(fieldVal)))

 

which in turn uses a constant:

 

#define CSL_ICSSINTC_HIER_ENABLE_HINT_MASK                      (0x000003FFU)

 

Applying the mask 0x000003FFU to the value 0x00000*C*03 gives the result 0x00000*0*03 (the value, which I see in the register ICSSG_ENABLE_HINT_REG).

 

Thus, using  PRUICSS_pruIntcInit (…) it is not possible to activate HOST_INT_10  to HOST_INT_19 because the mask  CSL_ICSSINTC_HIER_ENABLE_HINT_MASK  zeroes out bits 10-31 of the value which should be written in to the ICSSG_ENABLE_HINT_REG register.