The following assembly sequence generates the assembler warning shown below:

        DIV2PIF32 R0H,R0H 
        MPYF32    R1H,R5H,R3H
        MPYF32    R0H,R6H,R7H
    ||  MOV32     *-SP[2],R0H

WARNING! at line 209: [W9999] Register write access is in the delay
slot of a write of the same register
MPYF32 R0H,R6H,R7H

The DIV2PIF32 instruction ordinarily takes 3 cycles to complete prior to most other instructions. Therefore, the instruction "MPYF32 R0H,R6H,R7H" is indeed in its delay slot, causing the assembler to issue the warning. However, there is special pipeline behavior that causes the MOV32 instruction to read the output register value of DIV2PIF32 one cycle early. Because the MPYF32 instruction is performed in parallel with the MOV32, the MOV32 has already read the output of DIV2PIF32 before the MPYF32 writes it output register value, so there is no error with the MPYF32 writing to the same register one cycle later. The assembler does not detect this special circumstance and issues the warning.