[EXT_EP-7810] Should reject certain unitless instructions in parallel with certain other instructions Created: 18/Aug/13 Updated: 31/Jan/22 |
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| Status: | New |
| Project: | Embedded Software & Tools |
| Component/s: | None |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Bug | Priority: | Medium |
| Reporter: | TI User | Assignee: | TI User |
| Resolution: | Unresolved | Votes: | 0 |
| Remaining Estimate: | Not Specified | ||
| Time Spent: | Not Specified | ||
| Original Estimate: | Not Specified | ||
| Product: | Code Generation Tools |
| Internal ID: | CODEGEN-747 |
| OldID: | SDSCM00048041 |
| Found In Release: | C6000_8.2.0 C6000_8.3.0 C6000_8.1.0B1 C6000_7.4.0B1 |
| Description |
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C66x DSP CPU and Instruction Set Reference Guide (SPRUGH7 Nov 2010) section 3.8.12 (and subsections) has a long list of instructions that may not go in parallel, such as "DINT||NOP 5". The assembler does not detect some of these erroneous sequences and so therefore will not emit an error if such a sequence occurs in assembly. The C/C++ compiler does not produce these sequences when compiling C or C+, so the user of the compiler can safely assume these sequences won't occur if only compiling C or C+ code. For example, the assembler does not detect the following erroneous sequences: ; asm does not detect erroneous sequence
IDLE
|| NOP 2
; asm does not detect erroneous sequence
NOP 3
|| SWE
; asm does not detect erroneous sequence
RINT
|| MVC.S2 B0, TSR
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