In some cases, when a value is conditionally reset, an unconditional write may instead occur. For example, in the following code:

float16 get_float(int cond)

Generates:

VMVK32 .L2 0xff7fffff,VB0 ; No instruction predicate

Instead of the expected:

[!A0] VMVK32 .L2 0xff7fffff,VB0 ; Has instruction predicate

This behavior may occur with the following instructions in generated assembly. Lists are further subdivided by release, risk, and potential context:

1.1.0 and later; low risk; in the context of sequences of half vector accesses with VHHMV, VLLMV, and/or VHLMV:
VHHMV
VHLMV
VLHMV

1.1.0 and later; low risk; in the context of sequences of vector predicate moves with MV and MVPB:
MV
MVPP

1.1.0 and later; low risk; in the context of a following zero extension with EXTU:
ADDSP
ADDW
ANDNW
ANDW
DIVUW
DIVW
MODUW
MODW
MPYHW
MPYSP
MPYSUHW
MPYUHW
MPYWW
NANDW
NORW
ORNW
ORW
PCNTGATHERB
PCNTGATHERD
PCNTGATHERH
PCNTGATHERW
SHLW
SHRUW
SHRW
SUBRW
SUBSP
SUBW
XNORW
XORW

1.3.0 and later; low risk; in the context of sequences of packs and unpacks of vectors with VBPACKH, VBUNPKH, VHPACKH, VHUNPKW, VWPACKH, and/or VWUNPKD:
VSHRD
VSHRH
VSHRW

2.0.0 and later; low risk; in the context of repeated swaps of vector elements with VSWAPB, VSWAPH, VSWAPW, or VSWAPD:
VMV

3.0.0; moderate risk; in the context of initializing a vector predicate from a constant with MVK32, MVKU32, or MVK64:
MASKB
MASKD

3.0.0; moderate risk; in the context of widening a boolean vector with BITXPND:
MVDP
VMVPD
VMVPH
VMVPW

3.0.0; moderate risk; in the context of initializing a vector to all zeros with MVKU32, VPACKP2, VMVK32, VPACKL4, VMVK32, VDUP2B, VDUP4B, VDUP8B, VDUP16B, VDUP32B, VDUP2H, VDUP4H, VDUP8H, VDUP16H, VDUP2D, and/or VDUP4D:
VMVK32

3.0.0; moderate risk; in the context of initializing a vector to a 32 bit constant with VMVK32, MVK32, MVKU32, VDUP2W, VDUP4W, VDUP8W, and/or VDUPW:
VMVK32