[EXT_EP-10522] Partial failure observed for IPC test when MCU1_0 is enabled due to secure mode boot Created: 20/Aug/21 Updated: 02/Jun/23 Resolved: 02/Jun/23 |
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| Status: | Fixed |
| Project: | Embedded Software & Tools |
| Component/s: | None |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Bug | Priority: | High |
| Reporter: | TI User | Assignee: | TI User |
| Resolution: | Fixed | Votes: | 1 |
| Remaining Estimate: | Not Specified | ||
| Time Spent: | Not Specified | ||
| Original Estimate: | Not Specified | ||
| Product: | Processor SDK - Jacinto |
| Internal ID: | ADASVISION-4198 |
| Found In Release: | SDK_J7_07_00_00 |
| Fix In Release: | PROCESSOR_SDK_08.06.00 |
| Affected Platform/Device: | j721e-evm j721s2-evm j784s4-evm |
| Workaround: | IPC communication between A72 and MCU1-0 using the shared DDR region can be enabled by disabling cache from A72. For Linux, this can be done by adding the no-map property to the vision_apps_shared_region node. This will reduce the performance on A72 but allow this operation to occur. |
| Description |
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51.823387 s: REMOTE_SERVICE_TEST: Running test @ 0xae000000 of 1024 bytes size for CPU mcu1_0 !!! This test writes a pattern to shared memory and then mcu1-0 updates it by doing a +1 and A72 checks if value is +1. Core booted and IPC of messages worked, but shared memory access had data mismatch basically. |