Problem Statement: EMMC HS400 FIFO corruption 

Analysis (From IP vendor):

The rx clk reset being asserted is the only way to clear FIFO corruption when caused by a DLL glitch. The DLL may glitch on initial enable, or any subsequent disable/re-enable. So the mode switch intended to assert rx clk reset to clear possible FIFO corruption should be after the DLL enable to move to HS400. Based on our developer's description, it sounds like this is not the case. It is HS200 (enable DLL) -> HSSDR (disable DLL) -> HS400 (enable DLL).

Since this is a result of uninitialized flops, it is possible the second time through that they are now in a known state and this is why corruption is avoided but this does not fit the robust workaround as suggested by IP vendor and is based on empirical data only. It would need to look more like:

HS200 (enable DLL) -> HSSDR (disable DLL) -> HS400 (enable DLL) -> mode switch leaving DLL Enabled -> HS400 + 300ns wait -> begin transmission. 

Previously, based on our debugging, we provided a SW fix which can be found in the below commit

https://github.com/TexasInstruments/mcupsdk-core-k3/commit/83f745428c1be762b376f4513d982efdd2861ff4

But based on the above recommendation, the patch needs to be revised. 

Attached is the email chain where this is being discussed.