ICSSG: Inband bit is not cleared when link goes to 100M/1G from 10M

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    • Type: Bug
    • Resolution: Fixed
    • Priority: High
    • SITSW-7249
    • 11.00.00
    • 11.01.00
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      Port Tx stuck after multiple link down/up when PC sleeps.

      After the onsite debug - issue was found to be that the link first negotiates to 10M and them to 100M in the customer setup.

      In this scenario, the inband bit is set at 10M. But when handling 100M link up - this bit is not explicitly cleared. This is an invalid scenario for 100M and 1G where inband bit should not be set. This is thus, causing the TX port stuck during TX from ICSSG

      Fix:

      The fix for this issue in ENET LLD in the link up handling for 100M and 1G. The inband bit needs to be explicitly cleared.

      Corresponding PR:

      https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK/repos/enet-lld/pull-requests/993/diff#src%2Fper%2Ficssg.c

            Assignee:
            TI User
            Reporter:
            TI User
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              Created:
              Updated:
              Resolved:

                Connection: Intermediate to External PROD System
                EXTSYNC-5754 - ICSSG: Inband bit is not cleared w...
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