With the analysis of EMMC IP following are conditions to be met for EMMC and SD init sequence.

V1P8_SIGNAL_ENA

In Linux, we switch to full cycle timing by setting V1P8_SIGNAL_ENA before changing bus width for both eMMC and SD. Need to investigate why this is an issue; It is mentioned it does not matter when V1P8_SIGNAL_ENA is set and V1P8_SIGNAL_ENA is optional for eMMC. Further investigation shows that sequence in the driver is set according to SD spec. Could not find the same sequence in eMMC spec. The current solution aligned with HW team is to completely disable v1p8 for eMMC only since it is optional and leave as is for SD. Patches were send to fix V1P8_SIGNAL_ENA for eMMC in Linux source, uboot does not require this fix.

UHS_MODE_SELECT

If set, UHS_MODE_SELECT switches to full cycle timing and thus must not be set for LEGACY and HS modes. Patches were sent to fix UHS_MODE_SELECT in u-boot source. Linux does not have a problem with UHS_MODE_SELECT.

HIGH_SPEED_ENA

If set, HIGH_SPEED_ENA switches to full cycle timing and thus must not be set for LEGACY and HS modes. Patches were sent to fix HIGH_SPEED_ENA in u-boot source and Linux source.

OTAPDLYENA

If set, this will also switch to full cycle timing. Finished probing eMMC bus  to probe CLK and data to see of OTAPDLYENA affect full/half cycle timing. OTAPDLYENA does not affect full/half cycle timing, assumptions in the MMC driver can be left as is as long as  all other V1P8_SIGNAL_ENA, HIGH_SPEED_ENA, and UHS_MODE_SELECT are set appropriately.