The PMU on Cortex-R5 supports three event counters and one cycle counter. The PMU driver (init) enables all the four counters, and selects counter 0 for EVENT 1 (ICache Miss), counter 1 for EVENT 4 (DCache Access), and counter 2 for EVENT 3 (DCache Miss). The PMU_Init tries to write 0x1F (31) to PMSELR Register for EVENT 0xFF (cycle count), but the PMSELR doesn't accept any value above 0x2, so the previous value in PMSELR (0x2) is selected for EVENT 0xFF (cycle count) instead of EVENT 3 (DCache Miss). 

The profile data regarding EVENT 3 (DCache Miss) is not correct. The workaround is to comment out the code (Line #143 and 144) below in PMU_Init():