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Type: Bug
Resolution: Fixed
Priority: Low

Internal ID:
SITSW-4966
Found In Release:
09.00.00
Fix In Release:
10.01.00
Affected Platform/Device:

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am243x-evm
am64xx-evm

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am243x-evm am64xx-evm

CPU cache line size is wrongly documented.

https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/KERNEL_DPL_CACHE_PAGE.html

The following is the correct value.
CPU cache lines sizes for reference
R5F: 32B
A53: 64B

Assignee:: TI User
Reporter:: TI User
Votes:: 0 Vote for this issue
Watchers:: 2 Start watching this issue

Created:: 16/Oct/24 4:30 AM
Updated:: 16/Oct/24 4:30 AM
Resolved:: 16/Oct/24 4:30 AM

Connection: Intermediate to External PROD System

EXTSYNC-4811 - CPU cache line size is wrongly docu...
SYNCHRONIZED

Last Sync Date:

16/Oct/24 04:30 AM