[EXT_EP-13003] Compiler uses wrong NOP instruction encoding when filling gap caused by alignment before a loop Created: 28/Oct/25 Updated: 16/Dec/25 Resolved: 16/Dec/25 |
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| Status: | Fixed |
| Project: | Embedded Software & Tools |
| Component/s: | None |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Bug | Priority: | Medium |
| Reporter: | TI User | Assignee: | TI User |
| Resolution: | Fixed | Votes: | 0 |
| Remaining Estimate: | Not Specified | ||
| Time Spent: | Not Specified | ||
| Original Estimate: | Not Specified | ||
| Product: | Code Generation Tools |
| Internal ID: | CODEGEN-14666 |
| Found In Release: | ARMCLANG_2.1.0.LTS ARMCLANG_4.0.0.LTS ARMCLANG_3.2.0.LTS ARMCLANG_1.3.0.LTS |
| Fix In Release: | ARMCLANG_4.0.5.LTS* ARMCLANG_3.2.4.LTS* |
| Affected Platform/Device: | default |
| Description |
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Extract the attached test case to an empty directory. The source file int_handler.c has these lines ... void ISR_Init (void)
{
for(u_32 i = 0; i < ISR_COUNT; i++)
{
isr_fnc_table [i] = (u_32) ISR_default_function;
}
}
Build and disassemble ... % tiarmclang @options.txt int_handler.c % tiarmobjdump --source int_handler.o > dis.txt Inspect the disassembly to see ... 14: f2c0 0200 movt r2, #0x0
18: f000 e320 blx 0x40065c <ISR_Init+0x40065c> @ imm = #0x400640
1c: f000 e320 blx 0x400660 <ISR_Init+0x400660> @ imm = #0x400640
20: 180b adds r3, r1, r0
The instructions at offsets 0x14 and 0x20 are correct. Offset 0x20 is the start of a loop. The compiler issues a .p2align directive to align that address. The instructions at offsets 0x18 and 0x1c fill the alignment gap. They should be thumb2 mode NOP instructions. But instead, they are arm mode NOP instructions. |